Physical Design Overview

Physical design (Place and Route, PnR) takes the synthesized gate-level netlist and creates the physical layout of the chip — determining where every cell is placed and how wires connect them.

Physical Design Flow

Floorplanning: define chip area, power distribution, macro placement
Power Planning: design power grid (VDD/GND rings and stripes)
Placement: place standard cells (global → detailed → legalization)
Clock Tree Synthesis (CTS): build balanced clock distribution network
Routing: connect all cells with metal wires (global → detailed)
Timing Closure: fix timing violations through ECO, sizing, buffering
Sign-off: DRC, LVS, IR drop, electromigration analysis
GDSII Output: final layout file sent to foundry

Floorplanning

Floorplanning defines the physical boundaries of the chip and arrangement of major blocks:

Core Area: where standard cells and macros are placed
Die Area: includes core + I/O pads
Aspect Ratio: height/width of core
Utilization: % of core area occupied by cells (typically 70-80%)
Macro Placement: memory blocks, IPs placed manually for optimal routing

Clock Tree Synthesis (CTS)

The clock must reach every flip-flop at nearly the same time. CTS builds a balanced tree of buffers and inverters to minimize:

Clock Skew: difference in clock arrival times at different FFs
Clock Latency: total delay from clock source to FF clock pin

Routing Challenges

Issue	Cause	Fix
Congestion	Too many nets in a region	Spread cells, change floorplan
DRC Violations	Wire spacing/width rules broken	Reroute affected nets
IR Drop	Voltage drop in power grid	Add more power stripes/vias
Antenna Violations	Long wire collects charge, damages gate oxide	Add diodes or antenna fix cells

⚡ Interview Q: "What is the difference between DRC and LVS?" DRC = Design Rule Check (verifies layout follows foundry's manufacturing rules). LVS = Layout vs Schematic (verifies layout matches the netlist/schematic).